IDT70T633S10BCI【PDF 24/27 页】IC SRAM 9MBIT 10NS 256BGA

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IDT70T633/1S

High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Sleep Mode

The IDT70T633/1 is equipped with an optional sleep or low power

mode on both ports. The sleep mode pin on both ports is active high. During

normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the

port will enter sleep mode where it will have the lowest possible power

consumption. The sleep mode timing diagram demonstrates the modes of

operation: Normal Operation, No Read/Write Allowed and Sleep Mode.

For a period of time prior to sleep mode and after recovering from sleep

mode (t ZZS and t ZZR ), new reads or writes are not allowed. If a write or read

operation occurs during these periods, the memory array may be

corrupted. Validity of data out from the RAM cannot be guaranteed

immediately after ZZ is asserted (prior to being in sleep).

During sleep mode the RAM automatically deselects itself and discon-

nects its internal buffer. All outputs will remain in high-Z state while in sleep

mode. All inputs are allowed to toggle, but the RAM will not be selected and

will not perform any reads or writes.

JTAG Timing Specifications

t JCYC

t JF

t JCL

t JR

t JCH

TCK

Device Inputs (1) /

TDI/TMS

Device Outputs (2) /

t JS

t JH

t JDC

TDO

TRST

t JRSR

t JCD

x

5670 drw 23

t JRST

NOTES:

1. Device inputs = All device inputs except TDI, TMS, and TRST.

2. Device outputs = All device outputs except TDO.

JTAG AC Electrical

Characteristics (1,2,3,4,5)

70T633/1

3

3

Symbol

t JCYC

t JCH

t JCL

t JR

t JF

t JRST

Parameter

JTAG Clock Input Period

JTAG Clock HIGH

JTAG Clock Low

JTAG Clock Rise Time

JTAG Clock Fall Time

JTAG Reset

Min.

100

40

40

____

____

50

Max.

____

____

____

(1)

(1)

____

Units

ns

ns

ns

ns

ns

ns

t JRSR

t JCD

t JDC

t JS

t JH

JTAG Reset Recovery

JTAG Data Output

JTAG Data Output Hold

JTAG Setup

JTAG Hold

50

____

0

15

15

____

25

____

____

____

ns

ns

ns

ns

ns

NOTES:

1. Guaranteed by design.

2. 30pF loading on external output signals.

3. Refer to AC Electrical Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at

any speed specified in this datasheet.

5. JTAG cannot be tested in sleep mode.

5670 tbl 20

24

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